1. Field of the Invention
This invention relates to the reduction of insertion losses on a high frequency measurement system for load pull and noise testing of very low or very high internal impedance transistors. The test system consists of microwave load pull tuners, a wafer probe station and associated wafer probes, used in testing transistor and integrated circuit chips on-wafer.
2. Description of the Prior Art
On wafer load pull testing is important for R&D and production-run characterization of power transistor chips. Alternative solutions to wafer probing, like slicing and separating wafer chips individually and mounting (attaching and wire-bonding) them on alumina (Al2O3) dyes for testing is time consuming, expensive, destructive and inaccurate (due to the fact that wire bonding from an alumina substrate to a chip is difficult to characterize and to reproduce between different samples and between calibration and testing). As transistor chip size (total gate width) becomes larger in order to provide more RF power, the internal impedance of these transistors becomes very low (less than 1Ω) and has to be matched using microwave tuners. A similar situation occurs for very small and low noise transistors, where the internal impedance is very high (more than 2.5 kΩ). In both cases the corresponding reflection factors are very high and close to 1.
Presently, internal impedances of less than 1Ω have to be characterized. The actual status of load pull wafer probing equipment (including tuners, tuner-probe connections and probes) does not allow this because of the insertion losses introduced by the probes and the tuner-probe interconnections.
Whereas state of the art high reflection tuners allow impedances of less than 0.5Ω to be synthesized at the tuner reference plane, the losses of the probes and interconnections result in an impedance of 1.5Ω or more at DUT (device under test) reference plane. This deterioration corresponds to approximately a 0.25 dB insertion loss between the probe tip and the tuner test port, due to the probe loss itself and the interconnections between the probe and the tuner.
A typical load pull set-up configuration is shown in FIG. 1 (prior art).
The microwave tuner (6) is placed on the table of the wafer probe station (8) as close to the DUT (10) as allowed by other accessories of the probe station, like the microscope, which is needed to view the transistor chips and the wafer probes (11). The test port (12) of the tuner is connected at the junction (5) via a semi rigid or flexible RF cable (4) with the wafer probe head (1) at the junction point (3). The probe itself is supported by some auxiliary micro-positioners, not shown here, as they do not interfere with the RF behavior of the set-up.
Insertion losses incur at all points of the transmission structure starting at the tuner test port (12) and ending at the probe tip (11). Most of the losses (and residual reflections) occur at interconnections (5) and (3) because these interconnections include dielectrically filled support washers for the central connector pins, inside the dielectrically loaded coaxial cable (4) and inside the probe (1) at the point where the probe connector (3) transits over to an air-coplanar transmission line or a coaxial cable of the probe, depending on the nature of the probe used.
On wafer load pull testing of high power or low noise transistor chips is limited because the existing set-ups using passive electromechanical or electronic tuners cannot reach the reflection factors at DUT (device under test) reference plane, as required in order to effectively match the DUT. This “tuning range” limitation has a number of possible reasons:
1. Insufficient reflection amplitude tuning range of tuners
2. Lossy interconnections between tuners and wafer probes
3. Lossy wafer probes.
Item 1., the insufficient tuning range of the tuners, is not the subject of this patent and has been addressed elsewhere.
Experiments have shown that it is not possible to tune to microwave impedances below 1.5 to 2Ω at DUT reference plane using commonly available, passive, 50Ω based on-wafer load pull test systems, and this is increasingly insufficient for load pull testing of current medium power transistor chips.